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本帖最后由 13815898538 于 2019-6-19 16:42 编辑
从sx1212的datasheet(P14)看到如下内容
With an integer-N PLL architecture, the following criterion must be met to ensure correct operation:
.. The comparison frequency, Fcomp, of the Phase Frequency Detector (PFD) input must remain higher than six
times the PLL bandwidth (PLLBW) to guarantee loop stability and to reject harmonics of the comparison
frequency Fcomp. This is expressed in the inequality:
PLLBW ≤ Fcomp/6
.. However the PLLBW has to be sufficiently high to allow adequate PLL lock times
.. Because the divider ration R determines Fcomp, it should be set close to 119, leading to Fcomp≈100 kHz
which will ensure suitable PLL stability and speed.
问题:
从字面意思看,就是在设置R参数时,尽量往119靠,这样PLL可以比较稳定的工作,但是在需要设置多个频点时,
固定的R=119往往不够用,想请教一下,如果R值不设置为119,那么应该设置为比119大的值,还是比119小的值呢?
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